The present invention relates generally to the driving of video signals, and more specifically to a method and apparatus for providing digital video signals.
Prior to the advent of the laptop computers, display devices most commonly associated with computer systems were cathode ray tube (CRT) display devices. Such CRT systems projected images upon the screen of the display device based upon an analog input. Therefore, graphics adapters provided analog representations of images to the display devices. For example, analog RGB signals (red, green, blue) signals where provided to the display device in order to produce a desired image.
With the advent of laptop computers that used liquid crystal displays (LCDs), it was necessary to convert the analog video into a digital signal in order to accommodate the LCD drivers. As illustrated in FIG. 1, this was accomplished by having the video graphics adapter, or graphics device, produce the analog video signal it always had, and subsequently, a digital-to-analog converter within the display device converted the analog signal to a digital signal in order to provide the proper digital signal to the LCD display drivers. The use of an analog-to-digital converter in the laptop allowed for existing video driver technologies to be compatible with the newly emerging digital flat panel (DFP) display technology.
While the use of an analog-to-digital converter resulted in a readily available market of components capable of supporting DFP display devices, the need for compatibility resulted in additional costs. Specifically, a digital video signal generated by the VGA was converted to an analog signal (i.e. an RGB signal), transmitted, and converted from analog back into digital in order to be used by the digital flat panel display drivers. This resulted in the two conversions, one from digital-to-analog, and second from analog back to digital.
Prior art FIG. 2 illustrates another prior art implementation for transmitting video signals to the DFP display. Specifically, the VGA has been adapted to remove the digital-to-analog conversion step described with reference to FIG. 1. As described above, the digital flat panel display drivers receive digital data, therefore, there was no need for the dual conversions from digital-to-analog and analog-to-digital.
The prior art implementation of FIG. 2 did not convert the original digital data to an analog representation. Instead, the VGA of FIG. 2 merely provided a digital video signal to the display device. The digital video connections of FIG. 2 were accomplished using cables having a plurality of connection. In order to accommodate an RGB signal, the digital video cables used had up to 28 nodes. The 28 nodes were used in order to transmit the three 8-bit signals comprising the RGB colors and four control-bits. However, not only did this implementation require a very wide interface, the high refresh rate required more complex drivers in order to accommodate the full voltage swing necessary to provide the appropriate digital signals to the digital flat panel display. As a result, electromagnetic interference (EMI) concerns resulted. In addition to the wide interface, and EMI concerns, the result in wide interface cable resulted in the increase prices, and required a switching rate necessary to accommodate the DFP.
In order to address problems associated with the use of the wide interface, a serial transmission scheme was introduced. FIG. 3 illustrates one such scheme.
In FIG. 3, the video graphics adapter utilized an encoder for each of the digital signals. The encoder receives the digital data, and converts it to a serial data stream at an increased rate in order to provide each of the digital components to a decoder associated with the digital flat panel display. Generally, each byte of digital data is encoded on the VGA side into a 10-bit representation to be decoded on the DFP side. FIG. 4 illustrates a specific prior art implementation of the VGA encoder of FIG. 3. The VGA encoder receives a 10-bit encoded representation of one of the color signals. In the prior art implementation illustrated, two such 10-bit coded data are latcshed to form a 20-bit wide data word This 20-bit data word is divided into five four-bit segments, which are provided to a five-to-one four-bit multiplexor. The four-bit output of the multiplexor is received by a parallel-to-serial converter. The parallel-to-serial converter converts the received parallel data into a serial stream at a rate approximately 10 times the input reception rate of the 10-bit coded data. In order to accommodate the conversion, a phase locked-loop providing a four-stage multiphase clock is utilized. By controlling the selection of the data provided from the multiplexor to the parallel-to-senal converter it is possible for the prior art device of FIG. 4 to produce the desired transmission rate.
The prior art implementation illustrated in FIG. 4 utilizes a multiphase clock having four phases. One disadvantage with the implementation of FIG. 4 is that multiphase clocks having even number of phases are more costly in terms of design resources, and required silicon space than multiphase clocks having odd numbers of phases. Generally speaking, this is because it is not possible to use basic inverters for even-phased multiphase clocks. As a result, more costly designs must be used.
Therefore, a method and apparatus capable of overcoming the problems associated with prior art video drivers would be desirable.